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Lead ASIC DFT Engineer

1 month, 3 weeks ago
United States
Contract
Lead
Test Engineer
Quality Assurance and Testing
SOC
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Sapsol Technologies

Sapsol Technologies

Sapsol Technologies specializes in innovative business transformation by integrating ERP systems, AI, cloud computing, and DevOps, with a focus on S/4HANA implementation, system migration, and managed support services to optimize business processes and...

Internet Software & Services
51-250
Founded 2006
View All Jobs 57

Description

  • Architect, implement, verify, and debug advanced DFT solutions for ASIC and SoC designs.
  • Own DFT architecture across scan insertion, ATPG, MBIST/LBIST, JTAG, and boundary scan.
  • Lead post-silicon validation and debug efforts to resolve critical silicon issues.
  • Drive cross-functional debugging and issue resolution across engineering teams.
  • Evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
  • Perform scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Implement and verify MBIST solutions and support scan chain stitching and hierarchical DFT flows.
  • Support silicon bring-up and multi-domain integration on large SoC designs.

Requirements

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.

Interested in this position?

Apply directly on the company website

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